Non-volatile memory devices include a circuit, called a “page buffer”, dedicated to handle data information to be programmed into the memory and to be read from the memory. This circuit may also play a key role when memory array cells are erased. If nonvolatile memory information is accessed per page, there is a page buffer for each cell of the page.
The architecture of a page buffer according to the prior art is depicted in FIG. 1. The arrows illustrate the path of a signal representative of a bit read from a memory cell. In a read operation, a page buffer performs the following operations: a) it senses the program or erased state of the memory cell; b) at the end of the sensing operation, its output provides digital information which reflects the state of the read cell (for example, it is “1”, if the read cell is erased or it is “0” if the read cell is programmed); c) the state of the cell being read is stored into a latch within the page buffer (MAIN LATCH), so it can be retrieved later and read after the read algorithm is completed.
The page buffer is first reset (phase 1) by activating MRST; then a cell state is read through the source line SO (phase 2), and it is stored in the “main latch” when a signal MLCH is pulsed. Then (phase 3), the bit stored in the main latch (the voltage on the node QB_d) can be transferred to the IO buffers of the nonvolatile memory.
In a program operation, the page buffer executes the following three steps: 1) pattern storage; 2) pattern transfer; and 3) program pattern. After the program operation has been carried out, the program-verify operation may be executed. FIG. 2 illustrates the pattern storage operation in a known page buffer. Digital information that is to be programmed may be stored in the so called “cache latch”.
First, the cache latch is set to “1” (phase 1) by an activating signal CSET. If the data to be programmed is “0”, the cache latch is flipped (that is the logic content thereof is reversed) by asserting the signal nDI (phase 2); otherwise if the bit to be programmed is “1”, the signal nDI is not asserted and the cache latch is not flipped. In practice, asserting the signal nDI means that a “0” is to be programmed in the memory cell.
FIG. 3 illustrates the pattern transfer operation in the same known page buffer. The objective of this operation is to transfer the bit stored in the cache latch to the main latch. First the main latch is reset (phase 3) by pulsing the MRST signal; subsequently, information from cache latch is transferred to the SO node (phase 4) by activating a PDUMP signal, and it is stored in the main latch by pulsing MLCH. At the end of this phase, the node QB_d (that is the bit stored in the main latch) is set to “1” if the memory cell is not to be programmed (that is a “1” is to be written in the cell of the memory array), or it is set to “0” if the memory cell is to be programmed.
As soon as the bit to be written has been transferred to the main latch, the information stored in the cache latch is no longer relevant for the program operation; thus, a new bit to be programmed in a cell of a different page can be stored into the cache latch, thereby allowing the nonvolatile memory to “cache” two subsequent program operations.
As well known to a person of ordinary skill in the art, “caching” data insertion in the page buffer greatly improves program throughput of the nonvolatile memory because insertion of a bit to be written in a cell of page (i+1) is performed while carrying out the program algorithm for page (i). FIG. 4 illustrates the program pattern operation in the same known page buffer. The program pattern operation is triggered (phase 1) when the signal PGM is asserted, in detail, when the bit “1” is to be programmed, the cell bitline is forced to “1” (program inhibit). While when the bit “0” is programmed, the cell bitline is grounded.
FIG. 5 sketches a bitline of a FLASH NAND memory device and the respective page buffer. After the above discussed three steps have been carried out, the program-verify operation that follows checks whether the bit has been correctly written in the memory cell or not. In case of a FAIL, the previous three program steps are repeated at an increased voltage bias of the wordline WL. When verifying the cell, if the selected cell is programmed, which means the cell stores a “0”, then the cell is off, the voltage BLe remains high, and the voltage QB goes to 1 with a MLCH pulse. This makes the signal nWDO float.
On the other hand, if a “1” is to be programmed on the selected cell, QB is set to 1. When verifying the cell, if the selected cell is erased, i.e. the cell stores a “1”, then the cell is on, the voltage BLe switches low, and the cell may not affect the latched voltage QB. Thus, the level of the voltage QB corresponds to a “1”. This also makes the signal nWDO float.
The nWDO signals of the page buffers (PB) of the memory device may be merged according to a logic OR into a single nWDO signal, as shown in FIG. 6. The command CHECK is generated for enabling the generation of the flag PASS. The signals WDO are inverted replicas of the corresponding signals nWDO.
If all the selected cells are programmed successfully, all nWDO signals are floating. When the command CHECK switches high, then the flag PASS is high, and the program operation has been concluded successfully. Otherwise, if a bit “0” was to have been written in the cell but the selected cell is found to be erased, that is the cell that is not yet programmed (i.e. the cell is still conducting), and the voltage BLe switches low. This may not affect the value of the latched bit QB with the MLCH pulse, that is the bit QB remains at a level corresponding to “0”, thus the signal nWDO is high.
There is at least one nWDO signal that is at a high logic level, and the flag PASS is low; therefore, the failed program operation is flagged. In practice, during the program-verify operation, all the nWDO signals are checked simultaneously for generation of the PASS flag. The flow chart of FIG. 7 resumes the program-verify operation, and the flow chart of FIG. 8 continues the above four steps of the whole program operation.
Page buffers may also play a key role during other two operations that may not be allowed in nonvolatile memory devices, notably the “copy back program” operation and the “erase” operation, but this may not be relevant in this context and will not be considered. According to known techniques, the main latch may not reset before each program-verify operation. Indeed, the MRST signal may not be pulsed before each program-verify. This implies that, if during a program-verify operation, a page buffer latch is unexpectedly flipped, then the related cell may not receive further program pulses even if the relative cell has not reached the desired turn-on threshold. This situation is often referred in literature as “permanent inhibit” and may occur in the same way as when sensing a programmed cell (QB_d node is set to 1), for example, because of noise peaks or voltage surges on the source line SO.
U.S. patent application publication No. 2003/0117856 to Lee et al. discloses a nonvolatile memory device that has a page buffer including two banks of latches. This arrangement may cause a program fail if noise occurs on the common source line. Due to permanent inhibit, a cell where the threshold voltage has not yet reached a desired level (insufficiently programmed) could be erroneously recognized as a correctly programmed cell during a program-verify operation if disturbances are present during the execution of this step. This may cause the exclusion of the cell from receiving further program pulses used to reach the desired threshold voltage.
For this reason, Lee et al. discloses refreshing the bit stored in the main latch before each program-verify operation. In practice, the bit stored in the cache latch is copied in the main latch, then the program-verify operation is carried out for verifying whether the cell has been correctly programmed or not.
On the other hand, in order to retain the so-called “cache program” functionality, that is for loading in the cache latch a bit to be written in a cell of another page while the bit in the main latch is being written in the current page, the architecture of the page buffer may become more complicated. The “target pattern” to be programmed in page (i) should be stored in a register different from the cache latch, in order to make the latter available for storing the pattern of page (i+1).
FIG. 9 shows the two-register memory device of Lee et al., which includes a so-called “storing circuit” for providing an approach to the problems discussed above and for retaining the “caching” function. FIG. 10 is a simplified flow chart that describes the interaction among the three parts of the page buffer of Lee et al. The three parts are the “sense amplifier 2” (that corresponds to the “main latch” in our terminology), the “sense amplifier 1” (that corresponds to the “cache latch”), and the storing circuit. A weakness of the architecture disclosed by Lee et al. may be the fundamental issue of realizing a page buffer substantially insensitive to noise is still not achieved.
Tests carried out by the Applicants showed that it is still possible, though less probable than in the known page buffer of FIG. 1, that the bit stored in the cache latch of the page buffer of Lee et al. may be flipped by noise or eventual voltage surges on the source line.